FTL Layer Basic Operations

20 Jun

LLD contact FTL layer is responsible for the hardware layer and the top layer, which provides the basic operations, such as: block erase, page, pages read.

LLD layer supports various different NAND controller, to provide a standard interface, using the configuration shown in Figure 5.

LLD.C up to provide a unified interface, following by a different driver to achieve their respective functions, LLD_NAND.C realize NAND driver, LLD_EMU.C achieve the use of memory to simulate NAND device driver with analog NAND memory load balancing algorithm for testing has a very important significance, Figure 6 is the use of the results of the memory simulation drawn.

Results and analysis

After a lot of practical literacy and stress testing, the block device driver layer used in response to reader requests the use of the design process to avoid almost all because they do not read and write using DMA brought long occupied mutex kernel BUG generated . Shutting down the system starts again in the normal case mentioned above, the use of a fixed address using the read address from the mapping table method greatly improves the start-up speed, the system startup process is almost no wait here in the storage system initialization, the opposite If you do not use this method, you can clearly observed during system startup to initialize the storage system at this step happen wait, the wait time may vary with use NANDFlash further improve our approach to ensure the normal system shutdown in the case of greatly improve the startup speed. To test the load balancing algorithm, the 100MB file repeatedly erased 30,000 times, statistics endurance of each block, the results shown in Figure 6. Figure 6 can be drawn from our load balancing algorithm is very effective.


Through testing, the design of NAND storage system read and write data rate of 2MB / s or so, has better load balancing and garbage collection mechanism, which can adapt to the mainstream of today’s embedded devices storage capacity of literacy rate requirements; Since the entire Drivers are designed hierarchically by function, it is easier for subsequent maintenance

Retaining and upgrading work, the future direction of optimization mainly concentrated in address mapping and cache; Moreover, since the entire NAND storage system driver design is an independent design, with strong portability, scalability, good application value.


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