NAND Flash Memory Classification

14 Jun

NAND flash memory classification and technical characteristics

NAND flash memory can be divided into:

Single-layer (SingleLevelCell)

Multilayer (MultiLevelCell)

Flash translation layer FTL can be applied to the representative of Toshiba MLC chips, each cell stores two bits of data, there are four voltage levels. Represented by Samsung SLC, each cell stores one bit of data, there are two voltage levels. SI_, C technology and EEPROM is similar, but finds it difficult to have a big breakthrough capacity.

MLC Intel in September 1997 successfully developed the first, and the two bits of information into a floating gate, the use of different potential levels to distinguish data values. MLC chips can be stored per unit 2bit, capacity is equal to 2 times SLC chip architecture. Therefore MLC technology has significant advantages density, but its life compared with SLC, less reliability. While MLC technologically advanced, but also have cost advantages, but the disadvantages are: MLC block erase times (cycles) of l million, while the SLC is 10 million times; SLC unit only 0 or l two states, one lbit unit is damaged, missing data, and the MLC unit has four states, storage to be more precise control of the charging voltage of each memory cell, read the longer charging time is required to ensure the reliability of data is controlled four different states, a unit error occurs, it will lead 2bit data corruption, so the manufacturing process and control MLC chips have higher requirements.

However, MLC NAND technology is the future trend of development. The basic operation of NAND unit is a page (page), page includes data storage area, and OOB (outofband) free zone for ECC, wear leveling and other software overhead functions, both physically indistinguishable. Number of pages form a block erase (block), a series of blocks NAND chips, mostly small pages of SLC (512 +16) B page, block includes 32 pages, size 16KB: MLC will be large page size page expanded to IJ (2048 +64) B, each block contains 64 pages, size 128KB.

NAND in blocks erase operation, the erase block is one of the bit is set to “l”; write operation must be the blank area (all 1) for. NAND bidirectional data I / O port lines are generally eight, each transmission is (512 +16) * 8bit. But some NAND using 16 I / O lines of the design, such as Samsung K9K1G16UOA is 64M * 16bit chip NAND-type flash memory capacity 1Gb, the basic unit of data is (256 +8) * 16bit, or 512 bytes. In 16-bit mode, the instruction and the address using only the lower 8 bits, and only the upper 8 bits in the data transfer cycles are used. Addressing, through the I / O port address information transfer, each transfer 8 address information. Since relatively large capacity flash memory chips, a group of eight addresses only enough Addressing 256 pages, is clearly not enough, usually an address transmission needs of several groups, occupy a number of clock cycles. In addition to I / O port lines, there are six control signals: chip enable CE: write enable WE, responsible for data, address or instructions written NAND; read enable RE, allowing the output data; instruction latch CLE, is high when the rising edge of the WE signal, the instruction is latched into the instruction register NAND: address latch ALE, when ALE is high, the rising edge of the WE, the address is latched into the address register NAND; ready / Busy RB, is low then the NAND device is busy, the signal is open drain and requires a pull.

NAND multiplexed bus, thereby saving the number of pins, but also to the large volumes of chips transplanted into the same circuit board. NAND operations include: Page read mode l read pages of data area on page read mode 2 Read OOB area, page write / program, block erase, chip reset, read D, read status. 

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