FTL Management

26 Apr

The NFSD controller includes several components. The main terminal interface logic is responsible for connection to the host. Similarly, many high-performance NFSDs DRAMs as the cache locality principle, the use of data to improve performance. In the NFSD the cache controller manages the cache space. The last component in the the NFSD controller in a run in the intermediate software layer called FTL microcontroller.

This the FTL control of the overall hardware resources and soon NFSDs overall performance data, and therefore the precision of its performance. Since the channel and road are FTL management, we will discuss in Section II.C more FTLs. B NFM Chip Chip Chip Chip A NFM chip has a large array of memory cells for storing source data. The a NFM chips, these storage unit is hierarchical management. More specifically, each of the memory array includes a fixed block, each block is divided into a fixed page. A block is the basic unit of erase operation, and at the same time a page is the basic unit for read and write operations.

NFM chip compared to conventional non-volatile memory and magnetic storage has many advantages, but there are still some weak points. First, they have an erase and then write the interest, meaning that each block must be erased data inside even if only one page of data in it. Moreover, the time required to erase the block operation is a read or write operation several times. Therefore, frequent block erase operation will seriously degrade the overall performance. NFMS each block has a limited life span, usually measured as the maximum number of erase cycles.

To NFM reliability, write block of data to be as consistent as possible becomes very important. Finally, the read and write performance of the NFM chip asymmetric. For example, the write performance than read performance is 30% lower. Therefore, the write performance to enhance the the NFSD design a challenging problem.


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