FTL Schemes Overview

3 Apr

FTL scheme by Ban Ki-moon in 1995 applied for a patent, and NORbased by the PCMCIA standard flash memory after a few years . There is a NOR-based FTLs the problem, how to deal with in the first place.

When a page is covering the relevant entries in the flash memory needs to be updated in order to keep operating atomic and reliable. (Remember, page-level FTL plans to keep the entire mirror flash memory to reduce the overhead of mapping the SRAM table.) This is not difficult, NOR-based FTL, NOR-type flash memory programming (in bytes). Page list mapping the page, when necessary, be replaced by allocating, this mapping page can be updated (written to the first free entry of replacement of the same offset in the page list) several times the length of the list as long as they do not override The entire mapping [12,10].

DFTL (based on demand FTL) [10], another page-level FTL program, the first attempt before the transfer NORbased FTL NAND-type flash memory, replace part of the page is omitted. This plan, but efficient, facing serious reliability problems, because all information, if the system fails, the loss of SRAM. In this case, all data pages of the spare area needs to be scanned, until the system is restored to a consistent state. Therefore, DFTL appropriate, we believe that the case of flash memory, is regarded as a long-term reliable storage device.

Block-level FTL scheme

Against the patented dual FTL program in 1999, these plans are designed for NAND-type flash memory, also known as NFTLs. In this article, they will be cited as the NFTL-1 and the NFTL is-N. NFTL-1 is designed for flash memory, a spare area and NFTL-N is no such storage devices for each page.

When a page is covered NFTL-1 first allocation block replacement logic block, if not wrote: another one covering a page from the outset, the replacement block. Page written to replace the block, block replacement NFTL is scanning all the spare area, in the opposite order to find the most advanced and up-to-date version of the requested page. Fortunately, the use in the NAND-type Flash memory of the spare area is different addressing algorithm, optimizing the Quick Reference overhead, this search process is relatively low. On the other hand, some models of NAND flash memory

Memories when there is no spare area, support for fast searching, NFTL-N to maintain some of the logical blocks in the replacement block list necessary and write requests, for each logical page in the list of the first block of processing, and then the next one, remains in the block The offset of the same logical address. If the request to close all the pages in the list, set programming, a new data block allocation is appended to the list on the back.


Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

%d bloggers like this: