Information About FTL

30 Mar

Like other EEPROM devices, if a page has been programmed, the erase operation need to occur before the new data can be written. Make matters worse, the granularity flash erase operation is much larger than the read and write-in operation. If you in place update will be executed, we need to copy all the corresponding page in RAM block RAM update page, delete the block and write effective web pages. This update will not only reduce the performance of flash memory, but also can reduce the life of the chip, and brings potential consistency issues. In order to solve these problems, the outer places using updated. That is, when a page is covered, we assign a new free or delete pages, new data, and use a software layer called FTL change the physical location of the page.

In addition, about 10,000? 100,000 erase / write cycles, some blocks may become unstable failure.

Although a few blocks reserves the right to replace the damaged, these additional blocks will eventually be exhausted. FTL to a commonly used technology called “wear leveling”

Distribution erase flash longer life cycle in the entire memory.

From the database community work focuses on designing efficient indexing structure, such as BFTLμ-tree [29], [13], FlashDB [25], the LA-Tree [2], and FD-Tree [22]. Some of these technologies is built on the FTL, while others work directly on the original flash memory functions FTL, for example, address translation, garbage collection and wear leveling. In all cases, FTL flash-based technology is a key factor.

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